(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving Intra Level Dielectric (ILD) gap fill in creating a gate electrode structure.
(2) Description of the Prior Art
Basic to the creation of CMOS devices is the creation of Field Effect Transistors (FET) over active surface regions of a silicon substrate that are electrically isolated by regions of isolation such as Shallow Trench Isolation regions. The creation of FET devices starts with growing a layer of gate oxide over the surface of the substrate. A layer of gate material, typically comprising polysilicon, is deposited over the layer of gate oxide. The layers of gate material and gate oxide are patterned and etched, creating the structure of the gate electrode. Lightly doped impurity implantations are then performed into the surface of the substrate, self-aligned with the structure of the gate electrode, for the creation of Lightly Doped Diffusion (LDD) regions in the surface of the substrate. Gate spacers are then formed over sidewalls of the structure of the gate electrode after which relatively high-energy and high density source and drain impurity implantations are performed that are also self-aligned with the structure and further with the gate spacers of the gate electrode. Improved contact resistance can then be achieved by saliciding the surfaces of the source/drain regions and the top surface of the gate material of the gate electrode. After the process of salicidation has been completed, conductive contact plugs are established to the contact surfaces of the gate electrode by first blanket depositing a layer of dielectric over the created structure. Holes are created through the layer of dielectric, a conductive layer typically comprising metal is deposited over the surface of the layer of dielectric, filling the holes that have been created through the layer of dielectric and electrically contacting the contact points of the gate electrode structure. After excess conductive material has been removed from the surface of the layer of dielectric, points of electrical contact have been established by means of the conductive plugs that have been created through the layer of dielectric in alignment with the contact points of the gate electrode.
Improved semiconductor device performance continues to be achieved by reducing device dimensions, thereby reducing the paths that need to be traveled by electron charges in addition to reducing such factors are resistive loss over interconnect traces and parasitic influences that have a negative impact on device operational speed and performance. This continued reduction of the device elements imposes increased demands of accuracy and control in creating for instance CMOS devices. The invention specifically addresses the creation of gate spacers over sidewalls of the body of the gate electrode. As design rules continue to be reduced, the poly-to-poly spacing of the structure of the created gate electrodes continues to be reduced. Using conventional gate spacer design, the gap fill that is provided by the overlying layer of ILD may become a problem, specifically for CMOS designs in the deep-micron range of device features. A conventional approach of addressing this concern is to create L-shaped gate spacers, thereby allowing more of the ILD to penetrate between adjacent gate electrodes. This approach however has the negative effect of requiring a longer production time in addition with an increased thermal budget and an increased etching step. The invention addresses these concerns by providing a method that allows for the creation of a gate spacer having an L-shaped profile, which can be created while avoiding the previously stated negative aspects of creating such a gate spacer.
U.S. Pat. No. 6,277,683 B1 (Pardeep et al.) shows an L shaped spacer process and salicide process.
U.S. Pat. No. 6,235,597 B1 (Miles) discloses an L shaped spacer process and salicide process.
U.S. Pat. No. 6,090,691 (Ang et al.) shows an L shaped oxide spacer and salicide process.
U.S. Pat. No. 61025,267 (Pey et al.) shows a nitride blocker for a salicide process.
A principle objective of the invention is to provide gate spacers over the sidewalls of gate electrodes for gate electrode structures of deep sub-micron device dimensions.
Another objective of the invention is to provide a method of creating gate spacers over the sidewalls of gate electrodes such that gate separation and gate isolation is maintained even for extremely closely spaced gate electrodes.
Yet another objective of the invention is to provide a method of creating gate spacers that allows for an adequate amount of Intra Level Dielectric to penetrate between closely spaced gate electrode structures.
In accordance with the objectives of the invention a new method is provided for the creation of gate spacers over the sidewalls of a gate electrode structure. A patterned and etched layer of gate electrode material is formed over the active surface of a substrate, a layer of liner oxide is created, gate spacers are created.
Under he first embodiment of the invention, a layer of TEOS is deposited over the created structure over which a layer of nitride is deposited. The layer of nitride is etched, this etch is extended into an overetch creating openings through the layer of TEOS where this layer overlies the gate spacers. The gate spacers are then further etched.
Under the second embodiment of the invention, a layer of TEOS is deposited over the created structure. The layer of TEOS is etched, stopping on the silicon nitride of the gate spacers. The gate spacers are then further etched.